The invention relates to a semiconductor device comprising a semiconductor body provided with a programmable memory cell which comprises a bipolar transistor with an emitter and a collector of a first conductivity type mutually separated by a base of a second, opposite conductivity type, the emitter and the collector being coupled to a first and a second supply line, respectively, while the base is coupled to writing means through at least a control transistor provided with a control electrode.
Such a device is known from the Technical Digest of the International Devices Meeting 1988, pp. 44-47. The known memory cell comprises a vertical bipolar transistor with an n-type emitter and collector and a p-type base. The emitter and collector of the known memory cell are directly connected to a first and a second supply line, respectively, between which a constant potential difference of approximately 6 V is maintained during operation. The base is coupled to both reading and writing means through a PMOS transistor and a combined read/write line.
The operation of the known memory cell is based on the principle that electrons injected into the base are capable of freeing electrons around the base-collector junction and thus creating new free charge carriers. The charge carriers thus generated are then pulled away to either side of the depletion region under the influence of the prevailing electric field, thus providing an additional base current opposite to the base current externally supplied through the PMOS transistor.
When the base-emitter voltage (V.sub.BE) is sufficiently high, the additional base current gets the upper hand and the bipolar transistor continues to pass current, even if the external base current should drop out. The base-emitter voltage then remains at approximately 1 V. If only a comparatively low emitter-base voltage is applied, however, the externally supplied base current is the greater and the bipolar transistor will be cut off the moment the connection with the base is broken. The base-emitter voltage in that case is approximately 0 V. It is possible by applying a suitable potential to the base through the PMOS transistor to write the known cell into one of the two states, corresponding to a logic "1" or "0". To read out the actual memory state of a memory cell, the base-emitter voltage is detected in the known memory cell in a similar manner through the PMOS transistor and the combined read/write line.
The known device has the disadvantage that reading out of the memory cell takes place comparatively slowly. The combined read/write line and the circuit elements possibly coupled thereto in fact inevitably constitute a certain parasitic capacitance. When a memory cell is read, this capacitance must be completely charged before the base voltage appears at the read/write line. Since only a comparatively low base current serves as the charging current in the known device, reading of the known memory cell is comparatively slow.